More information on ULIS - ULtimate Integration on Silicon
The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains. Topics include, but are not limited to:
* Nanometre scale devices: physics, technology, characterisation techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
* CMOS scaling perspectives; device / circuit level performance evaluation; switches and memory scaling.
* New channel materials for CMOS electronics: strained Si, strained SOI, SiGe, GOI, III-V and high mobility materials for MOSFET; carbon based electronics; carbon nanotubes; graphene based devices.
* Thin gate dielectrics: first and second generation high-k materials for switches and memory.
* Alternative transistor architectures including PDSOI, FDSOI, DGSOI, FinFETs, MuGFETs, vertical MOSFET, IMOS and tunnel FET structures. Benchmarking of new architectures w.r.t. bulk CMOS.
* One dimensional and zero dimensional structures: nanowires, nanotubes, nanodots. Nanowire and nanotube based interconnects; nanocrystal based NVM memory cells.
* Variability and fluctuation phenomena in electronic switches and memory devices. Single electron, few electron, discrete dopant and discrete charge effects in scaled electron devices.
* Advanced physics based modelling and simulation of nanoscale switches and memory. First principle and ab-initio modelling of devices, materials and interfaces for CMOS.
* Quasi ballistic, ballistic and quantum transport in nanoscale devices. Compact modelling of nanoscale devices. modelling and management of thermal effects. Benchmarking of modelling approaches.
* Process characterisation through device parameter extraction, device and el