9 September, 2012    Lake Tahoe CA , 米国
The IEEE International Integrated Reliability Workshop (IRW) originated from the Wafer Level Reliability Workshop in 1982. The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, paper presentations, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and future semiconductor applications as well as ample opportunity for discussions and interactions with colleagues.

Hot reliability topics for the workshop include: SiGe and strained Si, III-V, SOI, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, organic electronics, emerging memory technologies and future "nano"-technologies, NEMS/MEMS, photovoltaics, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, product reliability and burn-in strategy, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, single event upsets.

IIRW 2012 will include a special resistive memory invited session. Resistive memory abstract submissions are also encouraged. Additional hot reliability topics for the workshop include: high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, and single event upsets.

開催地

Location: Stanford Sierra Conference Center
連絡先 Lake Tahoe , USA