Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) 2012
conferenze > Electrical Engineering conferenze > Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
October 21 - 24, 2012
Tempe AZ , Stati Uniti
EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis, synthesis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and CAD/design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Components, Packaging and Manufacturing Technology Society and IEEE Microwave Theory and Techniques Society. Authors are invited to submit papers describing new technical contributions related to the broad area of electrical performance of high-performance interconnect systems, covering:
• Emerging and advanced issues,
• New design techniques and innovative architectures
• Novel CAD concepts, methodologies and algorithms for modeling, simulation and optimization,
with emphasis on:
• System-level, board-level and on-chip interconnects
• High-speed channels, links, backplanes, serial and parallel interconnects, SerDes
• Low power mobile and personal applications
• Multiconductor transmission lines
• Memory and DDR interfaces
• Jitter and noise management
• Signal and thermal integrity
• Power integrity and power distribution networks (PDNs)
• Electronic packages and microsystems
• 3D interconnects, 3D packages, TSVs and MCMs
• Nano interconnects and nano structures
• RF/microwave packaging structures, RFICs, mixed signal modules and wireless switches
• Package-chip co-design
• Electromagnetic (EM) and EM interference modeling, simulation algorithms, tools and flows
• Macromodeling and model order reduction as it applies to electrical analysis
• Advanced and parallel CAD techniques for signal, power and thermal integrity analysis
• Measurement and data analysis techniques for system-level and on-chip structures.
• Emerging and advanced issues,
• New design techniques and innovative architectures
• Novel CAD concepts, methodologies and algorithms for modeling, simulation and optimization,
with emphasis on:
• System-level, board-level and on-chip interconnects
• High-speed channels, links, backplanes, serial and parallel interconnects, SerDes
• Low power mobile and personal applications
• Multiconductor transmission lines
• Memory and DDR interfaces
• Jitter and noise management
• Signal and thermal integrity
• Power integrity and power distribution networks (PDNs)
• Electronic packages and microsystems
• 3D interconnects, 3D packages, TSVs and MCMs
• Nano interconnects and nano structures
• RF/microwave packaging structures, RFICs, mixed signal modules and wireless switches
• Package-chip co-design
• Electromagnetic (EM) and EM interference modeling, simulation algorithms, tools and flows
• Macromodeling and model order reduction as it applies to electrical analysis
• Advanced and parallel CAD techniques for signal, power and thermal integrity analysis
• Measurement and data analysis techniques for system-level and on-chip structures.
Sede
Location: Tempe Mission Palms Hotel & Conference Center
Contatta
60 E 5th St. Tempe , USA
+1 (480) 894-1400
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