Workshop · Lake Tahoe, California

IEEE International Integrated Reliability Workshop (IIRW) 2013

Information Technology · General

Dates13–17 Oct 2013This edition has ended
VenueStanford Sierra Conference CenterLake Tahoe, California
RunningSince 2010Annual · 6 editions on record
Last checked12 Nov 2026Its old website no longer answers
This is the 2013 edition. It has ended. See IEEE International Integrated Reliability Workshop (IIRW)'s current page for the next dates.

Key numbers

Editions on record
6first in 2010

About IEEE International Integrated Reliability Workshop (IIRW)

The IEEE International Integrated Reliability Workshop (IRW) originated from the Wafer Level Reliability Workshop in 1982. The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, paper presentations, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and future semiconductor applications as well as ample opportunity for discussions and interactions with colleagues.

Hot reliability topics for the workshop include: SiGe and strained Si, III-V, SOI, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, organic electronics, emerging memory technologies and future "nano"-technologies, NEMS/MEMS, photovoltaics, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, product reliability and burn-in strategy, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, single event upsets.

IIRW 2012 will include a special resistive memory invited session. Resistive memory abstract submissions are also encouraged. Additional hot reliability topics for the workshop include: high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, and single event upsets.

From our listing of this edition. Details may have changed since.

Editions

YearDatesWhereExhibitorsVisitors
201513–17 Oct 2015Stanford Sierra Conference Center
Lake Tahoe, California
——
201413–17 Oct 2014Stanford Sierra Conference Center
Lake Tahoe, California
——
201313–17 Oct 2013Stanford Sierra Conference Center
Lake Tahoe, California
——
20129 Sep 2012Stanford Sierra Conference Center
Lake Tahoe, California
——
201116–20 Oct 2011Stanford Sierra Conference Center
Lake Tahoe, California
——
201017–21 Oct 2010Stanford Sierra Conference Center
Lake Tahoe, California
——

Past editions from the bvents archive (2008–2019) and organiser figures where they were published.

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